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Why does a single AND gate need 60 transistors?


Gate Output as a Switch?Best way to OR two LED signalsEarle Latch PropertiesWhy (not) put a resistor on FET gate?What does a logic gate output when powering down?Why would you need both a pullup resistor and a capacitor to ground on an IO pin?Why do some logic gate chips have a reversed pin layout?FETs: When does Input Capacitance and Gate Charge matter?How much current can a 74HC00 supply?Why does a full adder need an OR gate?













1












$begingroup$


Looking at the datasheet for the MC74VHC1G08, under the "features" section, it states Chip Complexity: FETs = 62.



Why does this IC need 62 transistors, while an AND gate can be made with only 6 transistors? What are the other 56 transistors being used for? My guess would be some sort of protection circuitry, but I am not sure.










share|improve this question











$endgroup$








  • 4




    $begingroup$
    How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
    $endgroup$
    – Elliot Alderson
    1 hour ago










  • $begingroup$
    Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
    $endgroup$
    – TimWescott
    1 hour ago










  • $begingroup$
    Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
    $endgroup$
    – Platytude
    1 hour ago






  • 1




    $begingroup$
    There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
    $endgroup$
    – Dave Tweed
    1 hour ago












  • $begingroup$
    @ElliotAlderson You're right - that should say 6, not 2.
    $endgroup$
    – eeze
    51 mins ago


















1












$begingroup$


Looking at the datasheet for the MC74VHC1G08, under the "features" section, it states Chip Complexity: FETs = 62.



Why does this IC need 62 transistors, while an AND gate can be made with only 6 transistors? What are the other 56 transistors being used for? My guess would be some sort of protection circuitry, but I am not sure.










share|improve this question











$endgroup$








  • 4




    $begingroup$
    How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
    $endgroup$
    – Elliot Alderson
    1 hour ago










  • $begingroup$
    Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
    $endgroup$
    – TimWescott
    1 hour ago










  • $begingroup$
    Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
    $endgroup$
    – Platytude
    1 hour ago






  • 1




    $begingroup$
    There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
    $endgroup$
    – Dave Tweed
    1 hour ago












  • $begingroup$
    @ElliotAlderson You're right - that should say 6, not 2.
    $endgroup$
    – eeze
    51 mins ago
















1












1








1





$begingroup$


Looking at the datasheet for the MC74VHC1G08, under the "features" section, it states Chip Complexity: FETs = 62.



Why does this IC need 62 transistors, while an AND gate can be made with only 6 transistors? What are the other 56 transistors being used for? My guess would be some sort of protection circuitry, but I am not sure.










share|improve this question











$endgroup$




Looking at the datasheet for the MC74VHC1G08, under the "features" section, it states Chip Complexity: FETs = 62.



Why does this IC need 62 transistors, while an AND gate can be made with only 6 transistors? What are the other 56 transistors being used for? My guess would be some sort of protection circuitry, but I am not sure.







digital-logic integrated-circuit logic-gates fet






share|improve this question















share|improve this question













share|improve this question




share|improve this question








edited 31 mins ago









StainlessSteelRat

3,531719




3,531719










asked 1 hour ago









eezeeeze

78111




78111








  • 4




    $begingroup$
    How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
    $endgroup$
    – Elliot Alderson
    1 hour ago










  • $begingroup$
    Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
    $endgroup$
    – TimWescott
    1 hour ago










  • $begingroup$
    Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
    $endgroup$
    – Platytude
    1 hour ago






  • 1




    $begingroup$
    There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
    $endgroup$
    – Dave Tweed
    1 hour ago












  • $begingroup$
    @ElliotAlderson You're right - that should say 6, not 2.
    $endgroup$
    – eeze
    51 mins ago
















  • 4




    $begingroup$
    How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
    $endgroup$
    – Elliot Alderson
    1 hour ago










  • $begingroup$
    Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
    $endgroup$
    – TimWescott
    1 hour ago










  • $begingroup$
    Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
    $endgroup$
    – Platytude
    1 hour ago






  • 1




    $begingroup$
    There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
    $endgroup$
    – Dave Tweed
    1 hour ago












  • $begingroup$
    @ElliotAlderson You're right - that should say 6, not 2.
    $endgroup$
    – eeze
    51 mins ago










4




4




$begingroup$
How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
$endgroup$
– Elliot Alderson
1 hour ago




$begingroup$
How can you make a CMOS AND gate with two transistors? I need a minimum of six, and I need a bunch more to buffer the output to drive a big off-chip load.
$endgroup$
– Elliot Alderson
1 hour ago












$begingroup$
Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
$endgroup$
– TimWescott
1 hour ago




$begingroup$
Does it actually have 62 transistors, or does ON have some formula to calculate sizing (like "tax horsepower" in the old days, only in the other direction)? Are all the transistors independent, or does it have a bunch of parallel transistors on the output for fan-out?
$endgroup$
– TimWescott
1 hour ago












$begingroup$
Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
$endgroup$
– Platytude
1 hour ago




$begingroup$
Protection circuitry in CMOS chips is usually accomplished by having diodes going from the input, to VCC and GND. I'm no expert in chip design, but I'd speculate it could have something to do with stepping the output signal drive up to higher levels. I've seen this is done by cascading inverters with progressively wider FETs to boost drive strength without sacrificing too much propagation delay. @ElliotAlderson that should be a question of its own, not a comment on an unrelated post.
$endgroup$
– Platytude
1 hour ago




1




1




$begingroup$
There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
$endgroup$
– Dave Tweed
1 hour ago






$begingroup$
There might not be literally 62 transistors; this might be a "normalized" number that gets plugged into some sort of reliability-predicting midel. That said, the datasheet says that it has "multiple stages", including an output buffer. And yes, input protection would count towards the transistor count, too.
$endgroup$
– Dave Tweed
1 hour ago














$begingroup$
@ElliotAlderson You're right - that should say 6, not 2.
$endgroup$
– eeze
51 mins ago






$begingroup$
@ElliotAlderson You're right - that should say 6, not 2.
$endgroup$
– eeze
51 mins ago












1 Answer
1






active

oldest

votes


















5












$begingroup$

There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:




  • As stated in the datasheet:



The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.





  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.


  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.


  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.


  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.


  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.



All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.






share|improve this answer









$endgroup$













  • $begingroup$
    Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
    $endgroup$
    – Toor
    30 mins ago












  • $begingroup$
    @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
    $endgroup$
    – Bimpelrekkie
    2 mins ago










  • $begingroup$
    The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
    $endgroup$
    – Bimpelrekkie
    1 min ago











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1 Answer
1






active

oldest

votes








1 Answer
1






active

oldest

votes









active

oldest

votes






active

oldest

votes









5












$begingroup$

There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:




  • As stated in the datasheet:



The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.





  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.


  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.


  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.


  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.


  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.



All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.






share|improve this answer









$endgroup$













  • $begingroup$
    Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
    $endgroup$
    – Toor
    30 mins ago












  • $begingroup$
    @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
    $endgroup$
    – Bimpelrekkie
    2 mins ago










  • $begingroup$
    The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
    $endgroup$
    – Bimpelrekkie
    1 min ago
















5












$begingroup$

There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:




  • As stated in the datasheet:



The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.





  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.


  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.


  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.


  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.


  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.



All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.






share|improve this answer









$endgroup$













  • $begingroup$
    Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
    $endgroup$
    – Toor
    30 mins ago












  • $begingroup$
    @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
    $endgroup$
    – Bimpelrekkie
    2 mins ago










  • $begingroup$
    The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
    $endgroup$
    – Bimpelrekkie
    1 min ago














5












5








5





$begingroup$

There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:




  • As stated in the datasheet:



The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.





  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.


  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.


  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.


  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.


  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.



All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.






share|improve this answer









$endgroup$



There can be several reasons why more than the minimum 6 MOSFETs (4 for an NAND + 2 for an inverter) are used in this IC:




  • As stated in the datasheet:



The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.





  • The output will be made using fairly large (not minimum size) transistors. There are always "folded" meaning multiple transistors are combined into one large one where drain and source diffusion areas are shared between two transistors. This behaves as one large transistor but could be counted as many if you want a higher transistor count.


  • The ESD protection at inputs and outputs of IC fabricated in modern CMOS processes often uses "grounded-gate MOSFETs" instead of the more traditional diodes.


  • An "ESD clamp" circuit is needed between the supply pins, such a circuit consists of a couple of transistors.


  • Digital circuits (like this AND gate) often need on-chip supply decoupling. These are called "decap cells". These are capacitors between the supply rails. These capacitors are mostly made by using the Gate-Drain/Source capacitance of Transistors.


  • In CMOS processes the MOSFETs are the most "basic" components, they are also the most controlled component and most flexible ones so IC designers prefer to use a MOSFET whenever possible.



All-in-all it is "quite easy" to need 62 transistors to make a seemingly simple function like an AND gate. That's also because this IC is "a bit more" than just a simple AND gate. The AND gates in more complex circuits like CPUs, microcontrollers etc. will often only use 6 transistors. But these aren't "stand alone" AND gates like this IC.







share|improve this answer












share|improve this answer



share|improve this answer










answered 53 mins ago









BimpelrekkieBimpelrekkie

49.7k243111




49.7k243111












  • $begingroup$
    Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
    $endgroup$
    – Toor
    30 mins ago












  • $begingroup$
    @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
    $endgroup$
    – Bimpelrekkie
    2 mins ago










  • $begingroup$
    The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
    $endgroup$
    – Bimpelrekkie
    1 min ago


















  • $begingroup$
    Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
    $endgroup$
    – Toor
    30 mins ago












  • $begingroup$
    @Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
    $endgroup$
    – Bimpelrekkie
    2 mins ago










  • $begingroup$
    The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
    $endgroup$
    – Bimpelrekkie
    1 min ago
















$begingroup$
Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
$endgroup$
– Toor
30 mins ago






$begingroup$
Is there a reason why you wouldn't just fab a larger transistor on the die instead of using multiple, smaller ones in parallel?
$endgroup$
– Toor
30 mins ago














$begingroup$
@Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
$endgroup$
– Bimpelrekkie
2 mins ago




$begingroup$
@Toor Yes, the size of the transistor. Say I need a W/L of 1000um/0.13um. That would mean a very wide ( 1mm) but very thin (less than 0.0005 mm) transistor which is unpractical, that would result in a very unusable size for the chip. What is preferred is a almost square chip (but a rectangle is OK as well). So we fold that transistor into for example 20 smaller ones of 50um/0.13um and combine that into a rectangular shape. Have a look at what that looks like here: zeptobars.com/en/read/…
$endgroup$
– Bimpelrekkie
2 mins ago












$begingroup$
The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
$endgroup$
– Bimpelrekkie
1 min ago




$begingroup$
The "folded" output transistor of this LDO is the structure between those two "blobs" (those are the bonding pads) in the upper-right part of the picture. Although this is an LDO, it would look similar on any IC where large MOSFETs are needed.
$endgroup$
– Bimpelrekkie
1 min ago


















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